FPGA IMPLEMENTATION AND DESIGN OF LOW POWER SEQUENTIAL FILTER

Abstract

 We will presents the design and FPGA implementation of sequential digital 8-tap FIR filter using a novel micro programmed controller based design approach. In the paper, the FIR filter is designed for operation controls by micro programmed controller. The proposed FIR filter will be coded in VHDL using modular design approach, and implement in Spartan-3E FPGA. The performance evaluation and synthesis results obtained through Xilinx ISE synthesis tool and functionally checked in Model sim module

Authors and Affiliations

Shivam Singh Sikarwa , Deepak Sharma , Vijay Kumar Sharma

Keywords

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  • EP ID EP137626
  • DOI -
  • Views 74
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How To Cite

Shivam Singh Sikarwa, Deepak Sharma, Vijay Kumar Sharma (2015).  FPGA IMPLEMENTATION AND DESIGN OF LOW POWER SEQUENTIAL FILTER. International Journal of Engineering Sciences & Research Technology, 4(4), 504-510. https://europub.co.uk/articles/-A-137626