Implementation of High Throughput Radix-16 FFT Processor
Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2014, Vol 4, Issue 7
Abstract
The extension of radix-4 algorithm to radix-16 to achieve the high throughput of 2.59 giga-samples/s for WPAN’s.We are also reformulating radix-16 algorithm to achieve low-complexity and low area cost and high performance. Radix -16 FFT is obtained by cascaded the radix -4 butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to its optimized pipelined structure. Besides, a new three-stage multiplier for twiddle factor multiplication is also proposed, which has lower area and power consumption than conventional complex multipliers
Authors and Affiliations
K Swetha sree , Mr. T. Lakshmi Narayana
Keywords
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