Implementation of Low Power SAR ADC Architecture Using Dual Tail Comparator
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 4
Abstract
The comparator is one of the fundamental building block in ADC applications This paper presents based on comparator analysis in the ADC design to optimize power and area, maximize speed and clock frequency. According to an analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator is proposed in the circuit of a dual tail comparator. Dual tail comparator is modified for low power and fast operations even in small supply voltages by adding few transistors, positive feedback during the regeneration is strengthened, it results to reduce delay time in the layout simulation results by using CMOS technology analysis. Power consuming for comparator is 0.252 mW and reducing 50% of area of the architecture due transistor sizing using 180 nm method and also improving latch regeneration speed.
Authors and Affiliations
C. V . Shincy*
Keywords
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- EP ID EP143198
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