Low Power Full Adder With Reduced Transistor Count
Journal Title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY - Year 2013, Vol 4, Issue 5
Abstract
Basic building blocks of most of the arithmetic and logic circuits are formed by XOR logic gate. This paper proposes a new 3T-XOR gate with significant area and power savings. In most of the digital systems adder lies in the critical path that increases the overall computational delay of the system. A new eight transistors one bit full adder based on 3T-XOR gate is presented. Simulations results utilizing standard 90nm CMOS technology illustrate a significant improvement in terms of number of transistors, chip area and propagation delay
Authors and Affiliations
M. Geetha Priya
Keywords
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