Low Power High Speed Two’s Complement Multiplier
Journal Title: International Journal of P2P Network Trends and Technology(IJPTT) - Year 2013, Vol 3, Issue 4
Abstract
To reduce the area of partial product array size and improve the speed which is generated by a radix-4 Modified Booth Encoded Multiplier is used. This reduction is possible without any increase in the delay of the partial product generation stage. This reduction provides faster compression of the partial product array and regular layouts in two’s complement multiplier. The proposed method is that the Radix-4 (Fixed-Width) Modified Booth Multipliers are used to achieve the low power and increase the speed by modifying the partial product matrix size. The Multiplier design implemented using Xilinx. The results based on a rough theoretical analysis and on logic synthesis showed its efficiency in terms of both area and delay. It is compared with Radix-4 (short bit-width) Modified booth encoded Multiplier.
Authors and Affiliations
P. Arulbalaji#1 , Mrs. K. Vanitha
Keywords
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