Memory Debug Technique Using March17N BIST
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 3
Abstract
A Memory Debug Technique plays a key role in System-on-chip (SOC) product development and yield ramp-up. Diagnosis technique plays a key role during the rapid development of the semiconductor memories, for Catching the design and manufacturing failures and improving the overall yield and quality. Conventional failure analysis (FA) based on bitmaps and the experiences of the FA (field application) engineer are time consuming and error prone. The increasing time-to-volume pressure on semiconductor products calls for new development flow that enables and product to reach a profitable yield level as soon as possible. This investigation on efficient diagnosis algorithms is very important due to the expensive and complex fault/failure analysis process. This MARCH based memory diagnosis algorithm which not only locate fault cells but also identify their types, using the proposed algorithm, stuck-at-faults, state coupling faults, transition faults can be distinguished. The demands in methodologies that allow FA automation thus increase rapidly in recent years. This algorithm proposes a systematic diagnosis approach based on failure patterns and functional fault models of semiconductor memories. By circuit level simulation and analysis, we have also developed a fault pattern generator. Defect diagnosis and FA can be performed automatically by using the fault patterns, reducing the time in yield improvement. The main purpose of this algorithm is for accelerating FA and yield optimization for semiconductor memories.
Authors and Affiliations
Ms. Zeenath
Keywords
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