N-BIT CMOS Comparator with Zero Crossing Detector Using Parallel Prefix Tree

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 N-BIT CMOS Comparator with Zero Crossing Detector Using Parallel Prefix Tree

Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 6

Abstract

 This paper provides an experience of new comparator model gives large range, with faster operation by converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic advantage by comparing Most Significant Bit (MSB) outcomes which is scheduled bit wise towards the Least Significant Bit (LSB). By comparing as the bits are equal and high speed zero detector circuit is used for decision module to reduce dynamic power wastage by eliminating unnecessary conversions in parallel prefix that render Nbit compression result following [log 4 N] + [log 16 N] + 4 CMOS cells. Core lead of this model is high speed and power effectiveness is maintained over a wide range. More than this, the design uses a standard reconfigurable VLSI topology that permits logical derivation of the input-output delay as a role of bandwidth. HSPICE form used in 32 bit comparator shows a defective case input output delay of 0.86ns and at most power consumption of 7.7mW using 0.15-μm TSMC technology at 1GHz.

Authors and Affiliations

V. Sidharthan *1

Keywords

High-speed Arithmetic unit High-speed Arithmetic unit

EP ID EP122395
DOI -
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