Performance Analysis of an NoC for Multiprocessor SoC
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 3
Abstract
In this work focus on ‘Network on chip’ and “Multiprocessor system on chip” applications its a guaranteed supporting for network process to reducing the circuit area, lower power consumption, low cost, and increases the performance. Network employs multi-stage network approaches on packet switching and pipelined circuit switching. Based on packet switching need more buffers, area should be high. To overcome the occupy more area by using pipelined circuit switching reducing some buffers in a multiple networks, The proposed network employs CHIPPER (Cheap-Interconnect Partially Permuting Router) technique for using “bufferless deflection router” method. This bufferless deflection routers to eliminate route buffers and cross buffers. So Removing buffers yields more energy in network on chip.
Authors and Affiliations
R. Ranjithkumar
Keywords
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