Performance Evaluation of Carry Select Adder-Review
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 11
Abstract
Arithmetic circuit is the fundamental block of many processor architectures such as digital signal processors and advanced microprocessor design. Adders form an almost mandatory component of every contemporary integrated circuit. Carry Select Adder (CSLA) used to achieve the fast addition operation, this is the high speed adders used in many DSP operations to perform accumulation operation. Speed is to be considered as an indispensable parameter, before that power dissipation is one of the most important design goals in many ICs. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. Several approaches have been proposed for the solution of this problem but development is currently still very much in progress. To overcome this problem Binary to Excess-1 Convertor (BEC), Sharing the Common Boolean Logic term and Gate-level modifications are used to improve the ADP parameters. The carry-select method is considered to be a good compromise between cost and performance in carry propagation adder design. Carry select adder is being able to calculate all the input bits nearly simultaneously. This article primarily deals the 4-,8-,16-,32-,64-Bit CSLA adders and various methods which is involved to reduce the Area, Delay, Power under several criteria.
Authors and Affiliations
M. Priyadharshini
Keywords
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