Power Efficient Design of BILBO using Various Sequential Elements for Low power VLSI Applications (Basic 5T-transistor and 5T- with MTCMOS)
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 2
Abstract
This paper enumerates low power design of BILBO(Built-In- Logic-Block-Observer) using Basic 5T-TSPC clocked latch and 5T-TSPC(MTCMOS) clocked latch.The clocked latches are basic building block to design the BILBO.The clocked latches consumes more power in the total power consumption of the BILBO.The power efficient 5T-TSPC(MTCMOS) clocked latch is designed from the Basic 5T-TSPC clocked latch. The BILBO is designed by using both Basic 5T-TSPC clocked latch and 5T-TSPC(MTCMOS) clocked latch.The design of BILBO by using 5T-TSPC(MTCMOS) consumes less power.The performance of BILBO is analyzed in terms of NumberofTransistors(NT),NumberOfClockedTransistors(NC),Power(P),Area(A).
Authors and Affiliations
P. Nagarajan
Keywords
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- EP ID EP111713
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