Reduced Complexity Wallace Multiplier using Parallel Prefix Adders
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 2, Issue 4
Abstract
The design of an area reduced and power substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. It works on the basis of “Acceleration of addition of summands”. The final two rows are summed with a carry propagating adder. A direct implementation requires a (2N propagating adder, where N – number of bits of operands. The objective of a good multiplier is to provide a physically compact, high speed and low power consuming chip. A syste the performance of the multiplier because the multiplier is generally the slowest element in the system. It is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is the major d In this paper we are using reduced complexity Wallace multiplier using parallel prefix adder to speed up the final addition
Authors and Affiliations
P. Krishnakumar
Keywords
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