VLSI Implementation of High Speed & Low Power Multiplier in FPGA
Journal Title: IOSR Journals (IOSR Journal of Computer Engineering) - Year 2013, Vol 15, Issue 3
Abstract
We known that different multipliers consume most of the power in DSP computations, FIR filters. Hence, it is very important factor for modern DSP systems to built low-power multipliers to minimize the power dissipation. In this paper, we presents high speed & low power Row Column bypass multiplier design methodology that inserts more number of zeros in the multiplicand thereby bypass the number of zero in row & Column as well as reduce power consumption. The bypassing of zero activity of the component used in the process of multiplication, depends on the input bit data. This means if the input bit data is zero, corresponding row and column of adders need not be addition & transfer bit in next row and column adder circuit. If multiplicand having more zeros, higher power reduction can be achieved. At last stage of Row & column bypass multiplier having ripple carry adder which are increase time to generate carry bit to transfer next adder circuit. To reduce this problem by using Carry bypass adder in place of ripple carry adder, then new modification of Row &column multiplier having high speed in comparison to simple row & column bypass multiplier, , the experimental results show that our proposed multiplier reduces power dissipation & High speed overhead on the average for 4x4, 8x8 and 16x16 multiplier
Authors and Affiliations
Prashant Kumar Sahu
Keywords
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