Novel Low Power Comparator Design using Reversible Logic Gates
Journal Title: Indian Journal of Computer Science and Engineering - Year 2011, Vol 2, Issue 4
Abstract
Reversible logic has received great attention in the recent years due to its ability to reduce the power dissipation which is the main requirement in low power digital design. It has wide applications in advanced computing, low power CMOS design, Optical information processing, DNA computing, bio information, quantum computation and nanotechnology. This paper presents a novel design of reversible comparator using the existing reversible gates and proposed new Reversible BJN gate. All the comparators have been modeled and verified using VHDL and ModelSim. A comparative result is presented in terms of number of gates, number of garbage outputs, number of constant inputs and Quantum cost.
Authors and Affiliations
Nagamani A N , Jayashree H V , H R Bhagyalakshmi
Keywords
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