On Fault Free Response Analysis For BIST
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2015, Vol 3, Issue 11
Abstract
High levels of coverage of classical and nonclassical faults require deterministic test sequences. In this paper, it is suggested that the deterministic test sequences be ordered in such a way that the fault-free output response is a trivial one that can be generated by simple on-chip circuitry, thereby obviating the need for test response compression.
Authors and Affiliations
Yogesh Singh| Research Scholar, Dr. K. N. Modi University, Rajasthan, INDIA singhyogesh2002@yahoo.co.in, Dr. Shafiqul Abidin| Professor, Department of Information Technology, HMR Institute of Technology & Management (Affiliated with GGSIP University), Hamidpur, Delhi, INDIA
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