On the Construction of Ground Bounce Noise Reduction Using Three - Step Wake-Up Partitioning
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 11
Abstract
In low power nanotechnology, the sub-threshold leakage occurs and it can be controlled by power gating techniques which does not affect the performance of the circuit. But the transitions of mode in the power gating takes place along with the large inrush/discharge currents which causes inductive noise on the power supply and the ground rails. The above issue can be tackled by slowly turning on the sleeping transistor, but introduces a fixed lower bound on the delay overhead, independent of the duration of the sleep period. The effect of changes in the internal circuit nodes at the time of wakeup is not been taken into account in the conventional methods. Under the observation of the internal nodes during sleep-to-active transition, can be partitioned into three distinct stages. This serves as the motivation for taking three–step turn on scheme that limits current flow while the gated block is in the metastable state. It strongly reduces power gating noise along with reduced wakeup time. The simulation is performed using full adder in 0.13µm technology as circuit under test. The further modifications are done to reduce the power consumption
Authors and Affiliations
Ms. N. Archana, Dr. K. Muthulakshmi, Ms. S. Nithya Devi
Keywords
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- EP ID EP392898
- DOI 10.9790/9622-0711055256.
- Views 135
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