Optimization of Voltage, Delay, Power and Area for 16 bit Cyclic Redundancy Check (CRC) in VLSI Circuits using 45nm Technology
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 9
Abstract
In Very-large-scale integration (VLSI) application area, delay and power are the important factors for any digital circuits. This paper presents 16 bit Cyclic Redundancy Check (CRC) mapped in Cadence Encounter(R) RTL Compiler Version v14.20-s013_1. By efficiently mapping into cadence tool, area, power and delay are decreased. The results of mapping are viewed using RTL synthesis tool in cadence VIRTUOSO at 45nm technology and 0.7V. Based on digital signal processing (DSP) architectures, the code for low power is generated using 16 bit Cyclic Redundancy Check (CRC).
Authors and Affiliations
Sudhakar Alluri, M. Dasharatha, B. Rajendra Naik, N. S. S. REDDY
Keywords
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- EP ID EP392439
- DOI 10.9790/9622-0709077884.
- Views 337
- Downloads 0
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