Performance Analysis of a 64-bit signed Multiplier with a Carry Select Adder Using VHDL
Journal Title: International Journal of Innovative Research in Computer Science and Technology - Year 2014, Vol 2, Issue 6
Abstract
This paper presents a performance analysis of carrylook-ahead-adder and carry select adder signed data multiplier we are using, one uses a carry-look- ahead adder and the second one uses a carry select adder. The main focus of this paper’s on the speed of the multiplication operation on these 64-bit multipliers which are modeled using verilog code, A hardware description language. The multiplier with a carry select adder has shown a better performance over the multiplier with a carry select adder in terms of gate delays. In this paper we are going to prove that the area and delay product of carry select adder gives better performance compare with carry-look-ahead adder signed 64 bit multiplier.
Authors and Affiliations
E. Deepthi, Gowdavelli village, O. Manasa
Keywords
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