Performance Analysis of Different Parallel CMOS Adders and Effect of Channel Width at 0.18um
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2012, Vol 1, Issue 8
Abstract
This paper investigates the designs of various adders implemented using CMOS technology like Full Adder, Carry select Adder, Ripple Carry Adder and Look-Ahead Carry Adder. Simulation is done using Tanner Tool at 0.18um, Addition time is critical to the design of a CPU. Mostly adders occupy critical path in many areas of microprocessor operation. There is a necessity of Fast adders in ALUs, for computing memory addresses, and in floating point calculations. Therefore, careful optimization of the adder is of the utmost importance. This optimization can be done either in the logic or circuit level way. Circuit optimizations manipulate transistor sizes and circuit topology to optimize the speed circuit is obtained. The designs are constrained by the factors such as maximum logic stages allowed for the design of a particular adder, fan-out restrictions, regularity of the design, etc. An extensive comparison of all designs is also reported in this paper to provide guidelines for the designers of adders. In particular, comparisons are made in terms of delay and area, where time is measured in terms of gate and transistor delays and area is measured in terms of number of gates of transistors required for the implementation. The comparative analysis will help designers to a have a better understanding of design metric (Power, Speed, Area) and to choose between trade-off of design. It has also been observed that by changing the width of CMOS, the delay parameter is improved if we move towards the ideal condition, whereas increasing the width drastically increases the size of CMOS used.
Authors and Affiliations
Akanksha Mandowara, , Mukesh Maheshwari,
Keywords
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