Possibilities of implementation of synchronous Ethernet in popular Ethernet version using timing and interference constraints
Journal Title: Leonardo Electronic Journal of Practices and Technologies - Year 2015, Vol 14, Issue 27
Abstract
Popular network architectures are following packet based architectures instead of conventional Time division multiplexing. The existed Ethernet is basically asynchronous in nature and was not designed based on timing transfer constraints. To achieve the challenge of next generation network with respect to efficient bandwidth and faster data rates, we have to deploy the network which has less latency. This can be achieved by Synchronous Ethernet (SyncE). In Sync-E, Phase Locked Loop (PLL) was used to recover the incoming jitter from clock recovery circuit. Then feed the PLL block to transmission device. We have to design the network in an unaffected way that the functions of Ethernet should run in normal way even we introduced timing path at physical layer. This paper will give detailed outlook on how Sync-E is achieved from Asynchronous format. Reference model of 100 Base-TX/FX was analyzed with respect to timing and interference constraints. Finally, it was analyzed with the data rate improvement with the proposed method.
Authors and Affiliations
KILARU Seetaiah , PULI Bhargava
Keywords
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