Power Analysis of Sequential Circuits Using MultiBit Flip Flops
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 11
Abstract
In today's VLSI technology, power is the major issue with shrinking technology. Clock will play important role in the integrated circuits. In this paper, Multi-bit flip flop technique has been introduced to reduce clock power. The idea behind this technique is that clock power savings can be achieved by using multi-bit flip flop cell with optimized design. Recent works have been proposing methods using multi-bit flip flops in standard cell based designs, where single-bit flip flops are replaced by multi bit flip flop cells during logic & physical synthesis. In this paper a comprehensive comparison between conventional flip flop and MBFF implementations of an industrial 90nm design has been done. Sequential circuits has been designed using single-bit flip flop and multi-bit flip flop.
Authors and Affiliations
Yarramsetti Ramya Lakshmi, Dr. I Santi Prabha, R Niranjan
Keywords
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