Power Minimisation in Scan Sequential Circuits Based On Best Primary Input Change Time

Apply

Power Minimisation in Scan Sequential Circuits Based On Best Primary Input Change Time

Journal Title: International Journal of Engineering and Science Invention - Year 2018, Vol 7, Issue 2

Abstract

Testing low power very large scale integrated (VLSI) circuits in the recent times has become a critical problem area due to yield and reliability problems. This research work lays emphasis on reducing power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the VLSI design flow. In the initial stage, this research work addresses power reduction techniques in scan sequential circuits at the logic level of abstraction. Implementation of a new best primary input change (BPIC) technique based on a novel test application strategy has been proposed. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by changing the primary inputs such that the smallest number of transitions is achieved. The new technique is test set dependent and it is applicable to small to medium sized full and partial scan sequential circuits. Since the proposed test application strategy depends only on controlling primary input change time, power is reduced with no penalty in test area, performance, test efficiency, test application time or volume of test data. Furthermore, it is indicated that partial scan does not provide only the commonly known benefits such as less test area overhead and test application time, but also less power dissipation during test application when compared to full scan. With a view to promote for power savings in large scan sequential circuits, a new test set independent multiple scan chain-based technique which employs a new design for test (DFT) architecture and a novel test application strategy has been indicated in this research work. The technique has been validated using benchmark examples and it has been shown that power is reduced with low computational time, low overhead in test area and volume of test data and with no penalty in test application time, test efficiency, or performance. The second part of this dissertation addresses power reduction techniques for testing low power VLSI circuits using built-in self-test (BIST) at RTL. First, it is important to overcome the shortcomings associated with traditional BIST methodologies. It is shown how a new BIST methodology for RTL data paths using a novel concept called test compatibility classes (TCC) overcomes high test application time, BIST area overhead, performance degradation and volume of test data, fault-escape probability, and complexity of the testable design space exploration. Secondly, power reduction in BIST RTL data paths is achieved by analyzing the effect of test synthesis and test scheduling on power dissipation during test application and by employing new power conscious test synthesis and test scheduling algorithms. Thirdly, the innovative BIST methodology has been validated using benchmark examples. Also, the research work states that when the power conscious test synthesis along with the test scheduling is combined with novel test compatibility classes and in this proposed research work, simultaneous reduction in test application time and power dissipation is achieved with low overhead in computational time.

Authors and Affiliations

Prof. Dr. G. Manoj Someswar, B. Babu Rajesh

Keywords

EP ID EP396362
DOI -
Views 86
Downloads 0