Power Optimization for a Datapath of A Genral Purpose Processor
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2012, Vol 1, Issue 6
Abstract
Data path is the core of the processor; it is where all computations are performed. The other blocks in the processor are supporting units. At present, most of the popular processor hardware synthesis tools give higher priority to delay. So the processor synthesis tools tend to generate data path architecture for faster implementation. With increasing importance of power reduction on a processor, it is becoming necessary to evaluate different data path architectures from the point of view of both delay and power. This work is aimed at characterizing various architectures of common operators for power, delay and area and selecting a particular low power architecture where delay is not critical. Multiplier Architecture that consists of both Array and Tree Multipliers, Mixed style Multiplier was found to be a suitable Architecture for better Performance. Performance evaluation was performed using Xilinx Power Analyzer and it was observed that the mixed style Multiplier gives an optimized power delay product.
Authors and Affiliations
Srinivasa Naidu Nalla, Kalpana Telkar
Keywords
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