Pre Layout And Post Layout Analysis Of Parallel Counter Architecture Based On State Look-Ahead Logic
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2013, Vol 2, Issue 2
Abstract
The main objective of this project presents designing a parallel counter architecture which is used to improve the operating frequency. It is a partitioning methodology which consists of two paths named as counting path and state look-ahead path. The function of counting path is used to find all counting states and which consists of three main modules. Module 1 is 2 bit counter and which generates the counting states for the rest of modules through the state look-ahead logic path. State look a head path is used to prepare the counting path’s next counting states, which triggers the all modules simultaneously. We implemented parallel counter and analyzed the parameters and layout is designed in cadence encounter tools.
Authors and Affiliations
Ulala N Ch Mouli Yadav , J. Samson Immanue
Keywords
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