Processor-Directed Cache Coherence Mechanism – A Performance Study
Journal Title: International Journal on Computer Science and Engineering - Year 2011, Vol 3, Issue 9
Abstract
Cache coherent multiprocessor architecture is widely used in the recent multi-core systems, embedded systems and massively parallel processors. With the ever increasing performance gap between processor and memory, there is a requirement for an optimal cache coherence mechanism in a cache coherent multiprocessor. The conventional directory based cache coherence scheme used in large scale multiprocessors suffers from considerable overhead. To overcome this problem we have developed a compiler assisted, processor directed cache coherence mechanism and evaluated. The approach is autoinvalidation based one that uses a hardware buffer termed Coherence Buffer (CB) and there is no need for directory. The CB method is compared in this paper with a self-invalidation based directory approach that employs a last touch predictor (LTP). Detailed architectural simulations of Distributed Shared Memory configurations with superscalar processors show that 8-entry 4-way associative CB performs better than the LTP based self-invalidation method as well as full-map 3-hop directory for five of the SPLASH-2 benchmarks under release consistency memory model. Given its performance, cost, complexity and scalability advantages, the CB approach is found to be promising approach for emerging applications in large scale multiprocessors, multi-core systems, and transaction processing systems.
Authors and Affiliations
H. Sarojadevi , S. K. Nandy
Keywords
Related Articles
- EP ID EP102955
- DOI -
- Views 116
- Downloads 0
Hamiltonian cycle and TSP: A backtracking approach
Backtracking is one of the strategies to reduce the complexity of a problem. Backtracking mainly useful when there is a no solution by going forward in that direction so we required backtracking from it to reduce the com...
Tracing and Straightening the Baseline in Handwritten Persian/Arabic Text-line: A New Approach Based on Painting-technique
In this research work, we propose to identify an imaginary line called baseline threading through the entire stretch of text-line, with reference to which the location of vertical extents of ersian characters could be a...
Task Scheduling Algorithm to Reduce the Number of Processors using Merge Conditions
Some task scheduling algorithms generate the shortest schedule, when its input DAG satisfies a specified condition. Among those scheduling algorithms, TDS algorithm proposed a DAG condition where allocation of two parent...
Invariant Moments based War Scene Classification using ANN and SVM: A Comparative Study
In this paper we are trying to classify a war scene from the natural scene. For this purpose two set of image categories are taken viz., opencountry & war tank. By using Invariant Moments features are extracted from...
An Improved Framework for Enhancing QoS in MIPv6
With the advent of technology, a large number of wireless and mobile devices are being connected to the internet increasingly giving the users access to the internet while on move. This mobility has been supported throug...