Pulsed Latch Based Area - Low - Delay Effective Shift Register
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 9
Abstract
With so many events happening in the world at a very fast pace the human race is in search for new technological advancements. There is a high demand for minutely packed power devices that have higher efficiency of area which has lead the industry of VLSI to venture into the unknown. As technology moves into these levels the power management requirement of the devices rise. This paper proposes allow power and area-efficient shift register using pulsed latches. The area and power consumption are made to reduce by substituting flip-flops with pulsed latches. The timing difficulty in the pulsed latches that originate out of the use of conventional single pulsed clock signal is taken care of by the use of multiple nonoverlap delayed pulsed clock signals. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches.
Authors and Affiliations
Sai Kumar, Radhika Reddy
Keywords
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