Radix-4 Encoder & PPG Block for Multiplier Architecture using GDI Techniqu
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2013, Vol 2, Issue 3
Abstract
A radix-4 encoder & partial product generator circuit is implemented that demand high speed and low energy operation. It is a good approach if we implement the multiplier as a hybrid architecture of the radix-4/-8 because the radix-8 mode has low power consumption capability, occupying less area and number of partial products obtained in this mode are less(N/3). But the detection of the 3B term while computing the partial products is very difficult and it is difficult to implement it on the FPGA board. So by comparing the performances of the two multipliers we suggest to go with the radix-4 multiplier. Compared to a conventional CMOS radix-4 encoder & PPG, the proposed circuit consumes 2.23% less power, 17.51% less average delay time with the use of only 74 transistors in comparison to conventional CMOS circuit which uses 204 transistors.
Authors and Affiliations
Ankita Dhankar, , Satyajit Anand,
Keywords
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