Real Time Zetta Bytes -Universal Memory ASIC SOC IP Core Design Implementation using VHDL and Verilog HDL for High Capacity Data Computing Processors like Cloud/Cluster/Super VLIW Parallel Distributing Pipelined Array Computing Processors
Journal Title: IOSR Journals (IOSR Journal of Computer Engineering) - Year 2016, Vol 18, Issue 5
Abstract
Abstract: The main intention is RTL Design Architecture and HDL Design Implementation of Zetta Bytes Memory ASIC SOC IP Core for Advanced Parallel Array Distributed Pipelined Array Computing /Cloud Computing / Super VLIW Computing/Cluster Computing Processors/very High Big Data Control Stations /Servers , Arrays of Data Servers, Interfacing for All Advanced Real Time Smart Computing Products-wireless , telecom , consumer, advanced processor and controller IP cores, Aerospace/Avionics ,Automotive , Industrial Automation ,Hi-Fi applications. Design Coding Implementation Done by Verilog HDL and VHDL , Simulationand Synthesizing , FPGA Front End Design Flow Implementation Done By Xilinx ISE 9.2i Software. Programming & Debugging Done through Xilinx Virtex /Kintex-7 FPGA Development Board/Kit.
Authors and Affiliations
P. N. V. M Sastry , Dr. D. N. Rao , Dr. S. Vathsal
Keywords
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