Reduced-Latency and Area-Efficient Architecture for FPGA-Based Stochastic LDPC Decoders
Journal Title: International Journal of Advanced Computer Science & Applications - Year 2017, Vol 8, Issue 7
Abstract
This paper introduces a new field programmable gate array (FPGA) based stochastic low-density parity-check (LDPC) decoding process, to implement fully parallel LDPC-decoders. The proposed technique is designed to optimize the FPGA logic utilisation and to decrease the decoding latency. In order to reduce the complexity, the variable node (VN) output saturated-counter is removed and each VN internal memory is mapped only in one slice distributed RAM. Furthermore, an efficient VN initialization, using the channel input probability, is performed to improve the decoder convergence, without requiring additional resources. The Xilinx FPGA implementation shows that the proposed decoding approach reaches high performance along with reduction of logic utilisation, even for short codes. As a result, for a (200, 100) regular codes, a 57% reduction of the average decoding cycles is attained with an important bit error rate improvement, at Eb/N0 = 5.5dB. Additionally, a significant hardware reduction is achieved.
Authors and Affiliations
Ghania Zerari, Abderrezak Guessoum
Keywords
Related Articles
- EP ID EP260002
- DOI 10.14569/IJACSA.2017.080707
- Views 100
- Downloads 0
Automatic Cyberbullying Detection in Spanish-language Social Networks using Sentiment Analysis Techniques
Cyberbullying is a growing problem in our society that can bring fatal consequences and can be presented in digital text for example at online social networks. Nowadays there is a wide variety of works focused on the det...
Explore the Major Characteristics of Learning Management Systems and their Impact on e-Learning Success
Today, there are many educational institutions and organizations around the world, especially the universities have adopted the e-learning and learning management system concepts because they want to enhance and support...
A Review of Towered Big-Data Service Model for Biomedical Text-Mining Databases
The rapid growth of biomedical informatics has drawn increasing popularity and attention. The reason behind this are the advances in genomic, new molecular, biomedical approaches and various applications like protein ide...
A Novel Hybrid Quicksort Algorithm Vectorized using AVX-512 on Intel Skylake
The modern CPU’s design, which is composed of hierarchical memory and SIMD/vectorization capability, governs the potential for algorithms to be transformed into efficient implementations. The release of the AVX-512 chang...
Multivariate Copula Modeling with Application in Software Project Management and Information Systems
This paper discusses application of copulas in software project management and information systems. Successful software projects depend on accurate estimation of software development schedule. In this research, three maj...