Reduced Number of Power Switches in Multi level Inverter Using SPWM Technique to Mitigate For SAG and SWELL
Journal Title: International Journal of Applied Engineering Research and Development (IJAERD) - Year 2018, Vol 8, Issue 1
Abstract
The study objective is to design and implement new topology symmetric for 3phase by focusing on reduced number of semiconductor devices in nine level Hybrid cascaded H-bridge multilevel inverter based on DVR. The main aim of this paper is to increase the number of levels with a low number of power switches and at the output without adding any complexity to the power circuit. The proposed work in inverter can generate odd level and it is used in SPWM technique for generating pulses. The main advantage of the new topology includes reduced switches from 48 to 36 and mitigation of sag, swell, analysis of the total harmonic distortion (THD),power factor improvement and high output voltage. The proposed topology results in reduction of occupied area, cost and simplicity of control system and it is wellsuited for high application. The performance of proposed work can be analysed through Matlab/simulink software. Finally, the results are compared at output side THD and PF conventional type and new topology is devised.
Authors and Affiliations
N EASHWARAMMA, J. PRAVEEN, M. VIJAYAKUMAR
Keywords
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- EP ID EP281613
- DOI 10.24247/ijaerdfeb20181
- Views 134
- Downloads 0
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