Reducing Power, Leakage of Standard-Cell Design using Stack Transistor Logic Design

Abstract

In this paper, a low leakage power optimizes CMOS layout designs. The approach is base on series-connected stack transistor technique. At first, the basic logic gate with conventional CMOS design and stack transistor base logic gate design is discussed. In stack technique, a two reduce size transistors are series connected with both gate terminals are interconnected to form single input.

Authors and Affiliations

Richa Singh, et al.

Keywords

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  • EP ID EP496567
  • DOI -
  • Views 130
  • Downloads 0

How To Cite

Richa Singh, et al. (2018). Reducing Power, Leakage of Standard-Cell Design using Stack Transistor Logic Design. International Journal of Engineering Innovations and Research, 7(2), 88-91. https://europub.co.uk/articles/-A-496567