Abstract

The dedicated short range communication (DSRC) is a protocol mainly used for intelligent transportation system. The information signals transmitted by this protocol are encoded by using either FM0 or Manchester codes. The code diversity between these two codes limits the designing of a VLSI architecture that supports the both. Hence this paper put forward a new VLSI architecture design which can be fully reused by using both the codes. This design based on similarity oriented logic simplification (SOLS) technique achieves an efficient performance compared with sophisticated works. This design flow can be attained in VHDL language by using Xilinx development board.

Authors and Affiliations