Review Of Bit-Parallel Polynomial Basis Multiplier Over GF(2m)
Journal Title: International Journal of Engineering and Science Invention - Year 2018, Vol 7, Issue 12
Abstract
In this paper, a review of all the bit-parallel polynomial basis multiplier for polynomials which cannot be factorized further (irreducible) has been presented. It is concluded that to decrease the hardware complexity, the best method is modified interleaved modular multiplication.This method is completely based on standard interleaved multiplication method. Two generic arbitrary elements are used to perform multiplication with interleaved modular reduction for irreducible polynomial defined in the field. A polynomial basis multiplier having bit parallel architecture which is scalable over GF(2 m ) is discussed. In comparison to past reported multipliers, it is having reduced hardware complexity and the power consumed is also very less.
Authors and Affiliations
Sakshi Devi, Rita Mahajan, Deepak Bagai
Keywords
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