Rtl Desing And Vlsi Implementation Of An Efficient Convolution Encoder And Adaptive Viterbi Decoder
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2014, Vol 2, Issue 11
Abstract
Error-correcting convolution codes provide a proven method to limit the effects of noise in digital data communication. Convolution codes are employed to implement forward error correction (FEC) but the complexity of corresponding decoder’s increases exponentially with the restraint length K. Sophistication Encoding with Viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive white Gaussian Noise. Here, we present a Convolution Encoder and Viterbi Decoder with a constraint length of 9 and code rate of 1/2. This is comprehended using Verilog HDL. It is simulated and synthesized using Modalism Altera 10.0d and Xilinx 12.1 ISE. The main goal of this paper is to design based Convolution Encoder and Viterbi Decoder which encodes/decodes the data. This architecture has simpler code and flexible configuration when compared to other architectures and saves silicon area through efficient device utilization which makes it favorable for fpga.
Authors and Affiliations
Thalakayala Eleesha| Student, M.Tech (VLSI), Sri Vasavi Institute Of Engineering And Technology, Nandamuru, V. G. Pavan Kumar| Assistant Professor, Sri Vasavi Institute Of Engineering And Technology, Nandamuru
Keywords
Related Articles
- EP ID EP16403
- DOI -
- Views 405
- Downloads 33
We propose a close real-time and cost-effective semantic questions based approach, called FAST. The thought behind FAST is to investigate and abuse the semantic connection inside and among datasets by means of relati...
Spyware prevention using graphical passwords
our future work will be based on Click-based graphical password schemes require a user to click on a set of points on one or more presented background images. With the Pass Points and to create users to a password by...
Renewable Energy System with High performance Hybrid Cascaded Inverter
In this paper, Renewal energy system with high performance Hybrid cascaded inverter is proposed. It is based on two kinds of power devices those are MOSFET and IGBT and also the cascaded inverter consists of three H-...
Design And Implementation of Modular Multilevel Inverter With Reduced Number Of Components
In this paper, utilizing H-connect topology a general course multilevel inverter for the execution of 49th level inverter and another calculation in producing all voltage levels for a 49th level with less number of dc...
The fundamental target of mathematics instruction is to invigorate one's instinct and logical point of view. Since the instinct is fuzzy, one can't be kept to two– esteemed logical considering. There ought to be som...