Rtl Desing And Vlsi Implementation Of An Efficient Convolution Encoder And Adaptive Viterbi Decoder
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2014, Vol 2, Issue 11
Abstract
Error-correcting convolution codes provide a proven method to limit the effects of noise in digital data communication. Convolution codes are employed to implement forward error correction (FEC) but the complexity of corresponding decoder’s increases exponentially with the restraint length K. Sophistication Encoding with Viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive white Gaussian Noise. Here, we present a Convolution Encoder and Viterbi Decoder with a constraint length of 9 and code rate of 1/2. This is comprehended using Verilog HDL. It is simulated and synthesized using Modalism Altera 10.0d and Xilinx 12.1 ISE. The main goal of this paper is to design based Convolution Encoder and Viterbi Decoder which encodes/decodes the data. This architecture has simpler code and flexible configuration when compared to other architectures and saves silicon area through efficient device utilization which makes it favorable for fpga.
Authors and Affiliations
Thalakayala Eleesha| Student, M.Tech (VLSI), Sri Vasavi Institute Of Engineering And Technology, Nandamuru, V. G. Pavan Kumar| Assistant Professor, Sri Vasavi Institute Of Engineering And Technology, Nandamuru
Keywords
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