Side-Channel Passive Attacks Implementation to Cryptographic Hardware Using FPGA
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2014, Vol 3, Issue 11
Abstract
This paper dealt with an FPGA based test bed used for injecting faults through clock glitches, to result in setup and hold violations. The UART interface is realized on FPGA to provide PC based controlling for this fault injection. The pre-build serial International Data Encryption (IDEA) algorithm synthesis models (.ngc files) will be used as test encryption algorithm. A main objective of our research is to develop an efficient method for protecting FPGAbased implementations of cryptographic algorithms through effective concurrent testing of various types of faults, including faults injected by the attackers. An essential part of this research is to develop a method and tool for the evaluation of susceptibility of FPGA-based circuits to fault injection attacks. In this paper, we present such a method and tool. It allows us to examine an FPGA-based circuit, in particular an implementation of a cryptographic algorithm, subjected to a fault injection attack based on clock glitching. The effectiveness of the proposed approach is assessed for the IDEA implementation.
Authors and Affiliations
K. Durga Rajasekhar, O. Sudha Bharathi, K. Sirisha, R. Satish Kumar
Keywords
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- EP ID EP28078
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http://www.ijrcct.org/index.php/ojs/article/view/604/pdf
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