Simulation & Implementation of Complex Multiplier using Vedic Mathematics
Journal Title: International journal of Emerging Trends in Science and Technology - Year 2014, Vol 1, Issue 5
Abstract
In VLSI technology speed optimization plays a vital role. So designing of high speed devices became necessary to fulfill the end user requirements. Generally the processor designing is mainly depending upon the MAC units. In that particularly multiplier architecture comes under crucial design. Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 Sutras (Formulae). In this paper the importance of Urdhva tiryakbhyam Sutra and Nikhilam Sutra are discussed. The design of complex multiplier designed using this sutra consists of Radix Selection Unit (RSU), Exponent Determinant (ED), Mean Determinant (MD) and Comparator. The multiplier shows the product of the provided inputs with reduced latency along with optimized power estimation. Transistor level implementation of Vedic Mathematics based 16-bit complex multiplier for high speed low power processor is reported in this paper. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by Xilinx sparten3E using standard 90nm CMOS technology for synthesis and simulation. The propagation delay of the resulting (16, 16) x (16, 16) complex multiplier was found to be 4ns and consume 81mW power. The implementation offered significant improvement in terms of delay and power from earlier reported ones
Authors and Affiliations
Aruna. M
Keywords
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