Single Bit Low Power Full Adder Cell using Substrate Bias Effect

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Single Bit Low Power Full Adder Cell using Substrate Bias Effect

Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 7

Abstract

Ultra low power portable electronic devices are the need of modern world. Portable devices need prolonged battery life, which can be achieved by reducing the power dissipation. Substrate bias effect is a leakage power reduction technique. It describes the changes in the threshold voltage with respect to change in source to bulk voltage. The substrate bias effect is used to control the leakage current. The reverse bias voltage widens the depletion region, due to which the threshold voltage increases. In this paper a single bit low power full adder has been proposed with substrate bias effect. Simulation of low voltage high performance hybrid single bit full adder cell also has been presented. By using the reverse biasing technique we have achieved power reduction in the single bit full adder cell. The power, delay and, power delay product (PDP) results have been obtained for proposed and existing designs with varying supply voltages. The proposed design shows PDP of 253.38fJ as compared to 277.23fJ of low voltage high performance hybrid single bit full adder cell at 1.8 Vdd. Simulation result show that the proposed design also performs better at varying temperature conditions. The power delay product has been also plotted versus the different reverse bias voltages applied in the proposed technique. All the work has been done in 180nm CMOS technology.

Authors and Affiliations

Sakshi Semwal, Dr. Jasdeep Kaur Dhanoa, Dinesh Kumar

Keywords

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EP ID EP391865
DOI 10.9790/9622-0707073538.
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