slugFPGA Implementation OF Iterative Log Multiplier Using Operand Decomposition For Image Processing Application
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2014, Vol 2, Issue 6
Abstract
Faster multiplier is the vital procedure mainly for DSP and image processing application. Log multiplier converts the multiplication into addition, hence speed up the multiplication. Mitchell’s approximation based log multiplier does this but with errors. OD-Mitchell reduces the AEP (Average Error Percent) while the iterative Mitchell reduces the MPE (Maximum Possible Error).This project focuses on combining both the method to improve AEP and MPE. Further this multiplier is used in case of Gaussian filter to improve PSNR (Peak Signal To Noise Ratio).Hence the accuracy is improved here. The hardware implementation is done by using the FPGA board. The simulation is done using XILINX 14.5 and Modelsim.
Authors and Affiliations
Pragyan Paramita Mohanty, Mrs. Annapurna K. Y
Keywords
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- EP ID EP18303
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