slugHierarchical Power and Activity Analysis of an Clock Gated ALU
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2014, Vol 2, Issue 5
Abstract
System-level or architectural-level power analysis is an important phase of SoC or NoC, to estimate and evaluate power at the early stage of the design phase. Power at the hierarchical level depends on the lower-level design modules, its signal rates, average activity, and also the fanout of the modules. In this paper, the power obtained by the low-level modules inturn reflecting the top-level is analysed for an 16-bit ALU. This paper also makes the analysis of the average fanout and average activity of the blocks of ALU. These parameters reflect the performance of the ALU. The fanout report, activty report is obtained for the devices or cells utilized for the ALU with and without using the clock gating technique . It is observed that activity rate with clock gating for the arithmetic module is higher than without the clock gating, while for the logic module it is less.
Authors and Affiliations
Roopa Kulkarni, Dr. S. Y. Kulkarni
Keywords
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