Soft Error Tolerance in Memory Applications
Journal Title: International Journal of Advanced Computer Science & Applications - Year 2018, Vol 9, Issue 8
Abstract
This paper proposes a new method to detect and correct multi bit errors in memory applications using a combination of a clustering approach, Bit-Per-Byte error detection technique, and Majority Logic Decodable (MLD) codes. The likelihood of soft errors accelerates with system complexity, reduction in operational voltages, exponential growth in transistor per chip, increases in clock frequencies, breakdown of memory reliability and device shrinking. Memories are the sensitive part of a computer system. Soft errors in memories may cause an instruction to malfunction. Several techniques are already in practice to mitigate the soft errors. Majority logic decodable codes are proved as effective for memory applications because of their ability to correct a massive number of errors. Since memories are used to hold large number of bits that’s the restraint of Majority logic decodable codes method, so we emphasize on the size of data word in this method. The proposed method aims to detect and correct up to seven bit errors with lesser computational time. It works in an efficient manner in case of adjacent errors which is not possible in Majority logic decodable codes (MLD). It is delineated by Experimental reviews that the proposed approach outperforms existing dominant approach with respect to number of erroneous bit detection and correction, and computational time overhead.
Authors and Affiliations
Muhammad Sheikh Sadi, Md. Shamimur Rahman, Shaheena Sultana, Golam Mezbah Uddin, Kazi Md. Bodrul Kabir
Keywords
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- EP ID EP375886
- DOI 10.14569/IJACSA.2018.090839
- Views 67
- Downloads 0
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