SPAA AWARE ERROR TOLERANT 32 BIT ARITHMETIC AND LOGICAL UNIT FOR GRAPHICS PROCESSOR UNIT

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SPAA AWARE ERROR TOLERANT 32 BIT ARITHMETIC AND LOGICAL UNIT FOR GRAPHICS PROCESSOR UNIT

Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 5, Issue 7

Abstract

Arithmetic and logical unit are responsible for all computationally intensive task which determines the speed and reliability of a processor. In other word we can say ALU is the brain of a processor. Nowadays every portable devices are battery operated so primary concern of those devices are low power consumption. But at the same time we want higher performance also so that there should not be any lag while using those devices. Graphically intensive application demands more resources and at the same time demand more power. Optimization between speed of operation and power consumption is the key challenge in design paradigm. The performance increase can be achieved by increasing clock frequency, but it leads to some other issues such as overheating, leakage etc. Instead, We approach to exploiting parallelism at the architecture level, which significantly increase throughput without compromising on power. Instead, using single, powerful CPU, we can add a cluster of less powerful CPU on a single chip, which combinatorically gives better performance. In proposing work we present architecture of 32 bit ALU for graphics processors. We have designed and implemented multicore processor based on 8bit ALU unit, which is specifically designed for low power consumption. The synthesized architecture is implemented in Verilog HDL. Analysis is performing on FPGA Artix-7 (Field Programmable Gate Array) level.

Authors and Affiliations

Kaushal Kumar Sahu*,

Keywords

ALU Verilog FPGA Artix-7 System design ALU Verilog FPGA Artix-7 System design

EP ID EP154263
DOI 10.5281/zenodo.56917
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