Study on Performance of Vedic Multiplier Based On the Adders Used
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 5
Abstract
In ALUs, DSPs, and microprocessors addition and multiplication are most commonly used arithmetic computation. Multipliers play a key role in determining the overall performance of the system design. But multipliers use more processer time thus diminishing the overall system performance. Thus to maintain high throughput it is important to select high speed multipliers in terms of low area, low power, less delay. Multiplier involves generation of partial products and also their addition. Vedic mathematics is considered to be a powerful tool for enhancing the calculation speed. It speeds up the multiplication by generation of partial product. Vedic multiplier is considered to be faster multiplier when compared to the other multipliers. The speed of multipliers is based on the adders used for the addition of partial products. In this paper performance of Vedic multipliers are discussed based on the adders used.
Authors and Affiliations
Rose Ann Mathew, Shruthi. H. Shetty, Ashwath Rao, Deepthi Dayanand
Keywords
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