Systematic Design of High-Speed and LowPower Digit-Serial Multipliers VLSI Based

Abstract

Terms of both latency and power Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial architectures obtain using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of digit-serial architectures is presented based on a novel design methodology. This methodology permits bit-level pipelining of the digit-serial architectures by moving all feedback loops to the last stage of the design. This enables bitlevel pipelining of digit-serial architectures, thereby achieving sample speeds close to corresponding bitparallel multipliers with lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The proposed approach is applied to the design of various multipliers which form the backbone of digital signal processing computations. The results show that for transformed multipliers with smaller digit sizes (_4), the singly-redundant multiplier consumes the least power, and for larger digit sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit size for least power consumption in type-I and type-III multipliers is _p2W, where W represents the word length. Among the bit-level pipelined digit-serial multipliers, it is found that the redundant multiplier offers the best choice in consumption The proposed digit-serial multipliers consume on average 20% lower power than the traditional digit-serial architectures for the non pipelined case and about 5–15 times lower power for the bit-level pipelined case.

Authors and Affiliations

Ms. P. J. Tayade and Dr. Prof. A. A. Gurjar

Keywords

Related Articles

MULTIRATE SIGNAL PROCESSING APPROACHES

Multirate Signal Processing studies Digital Signal Processing systems which include sample rate conversion. This technique is used for systems with different input and output sample rates, but may also be used to imple...

Integration of Artificial Neural Network and GIS for Environment Management

The purpose of a GIS is to provide both the individual and organization with increased knowledge and understanding of spatial data. Often GIS users overlook the „decision making‟ capability these systems can provide, i...

Development Of Error Control Coding Technique In Digital Communication System

During digital data transmission in digital communication system, noise is added and physical defects in the communication medium can cause random errors during data transmission. Error coding is a method of detecting...

A study on role of transformational leadership behaviors across cultures in effectively solving the issues in Mergers and Acquisitions

As and when Merger and acquisition comes to a discussion, financial aspects will take a lead and less will be the humanitarian approach. By understanding this fact there are considerable research work which started foc...

Challenges in Indian Financial Sector to become Economic Super Power in the Coming Decade

Presently India is borrowing heavily from World Bank and ADB for Government Projects. The Private ventures are looking for FDIs but the ceiling is restricted by government policy. Hence a considerable fiscal from GDP i...

Download PDF file
  • EP ID EP26662
  • DOI -
  • Views 319
  • Downloads 6

How To Cite

Ms. P. J. Tayade and Dr. Prof. A. A. Gurjar (2012). Systematic Design of High-Speed and LowPower Digit-Serial Multipliers VLSI Based. International Journal of Engineering, Science and Mathematics, 2(5), -. https://europub.co.uk/articles/-A-26662