Systolic Architecture for High Speed FIR Filter Using VLSI Technology
Journal Title: INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY - Year 2015, Vol 14, Issue 11
Abstract
The tremendous growth of computer and Internet technology wants the data to be processed athigh speed. Low power consumption, high throughput and optimized hardware are the most important design criteria’s for VLSI implementation. This project gives an efficient design of high speed FIR filters using systolic architecture. In this paper we have implemented 7th,8th,11th order FIR filter with 8 bit normalized input. To obtain efficient results we have selected B1 design from all the designs of systolic arrays.GF (28) multiplier and XOR adder are used for multiplication and addition in filter. Hamming window technique is used to derive the filter coefficients. The coefficients of filter are found out using Matlab. The FIR filter architecture is effectively synthesized and simulated using Xilinx ISE 8.1i in VHDL and Modelsim simulator. Maximum frequency, timing simulation delay and number of slices were used as performance metrics. The results obtained are compared with the existing results achieved for FIR filter, thus our work proves that the objective of high speed has been achieved successfully with the use of minimum number of slices.
Authors and Affiliations
Monika Dattatraya Wavhal
Keywords
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- EP ID EP650734
- DOI 10.24297/ijct.v14i11.1805
- Views 75
- Downloads 0
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