Techniques for Cache Improvement
Journal Title: IOSR Journals (IOSR Journal of Computer Engineering) - Year 2018, Vol 20, Issue 5
Abstract
Personal data caches have been rendered ineffective in the process of reducing the median memory lag in multiprocessors, as is the case in single-processors, due to the distribution of data amongst processors, and further related to a cache issue. Therefore, a multitude of processors have been implemented with the purpose of sustaining cache improvement in the presence of large-scale shared data processes; thus it is difficult to perform a comparison of implementation implications and performance. This paper is penned with the purpose of aiding future computer architects comprehend the opportunity costs involved as well as contemporary cache improvement processes, and other design-related problems. Current design problems include: 1) the improvement strategy, which provides the means for cache data access to be detected. 2) An enforcement strategy, which dictates that updates and validations are run to ensure that outdated cache entries are not referenced by a processor 3) Block sharing information precision and how it can be altered to lessen the implementation costs and to increase the performance of the memory system.
Authors and Affiliations
Dr. Mohammad Mahmood Otoom, Dr. Khalid Nazim Abdul Sattar
Keywords
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