Test Optimization of 2D SOC using Enhanced ACO Algorithm
Journal Title: International Journal of Computational Engineering and Management IJCEM - Year 2015, Vol 18, Issue 3
Abstract
With advancement in technology it is possible to design complex chips. To reduce the complexity of a chip, embedded cores based system-on-chip are being advocated. These complex chips require high test data volume which further increases the test application time. The cost of testing is dependent on total test application time. To reduce test application time, testing of cores should be done concurrently. This paper first proposes test solution using Ant Colony Optimization algorithm and then compares its performance using test time. Fork and merge technique is used for TAM sharing. Test time and TAM width of cores is selected using wrapper design algorithm. Experimental results on ITC’02 benchmark circuits for different widths of Test access mechanism (TAM) wires proves the effectiveness of one algorithm over the other.
Authors and Affiliations
Naveen Dewan and Harpreet Vohra
Keywords
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