The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications

Journal Title: Annals of Emerging Technologies in Computing - Year 2019, Vol 3, Issue 3

Abstract

This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA) implementation. Moreover, its propagation delay and adder units count are respectively about 31% and 8.5% lower than the implementation using the bypassing RCA multiplier. All of these simulations were carried out using the HSPICE circuit simulation software in 0.18 μm technology at 1.8 V supply voltage. The proposed design is thus highly suitable in low power drain and high-speed arithmetic electronic circuit applications.

Authors and Affiliations

Mohsen Sadeghi, Mahya Zahedi, Maaruf Ali

Keywords

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  • EP ID EP594476
  • DOI 10.33166/AETiC.2019.03.003
  • Views 93
  • Downloads 0

How To Cite

Mohsen Sadeghi, Mahya Zahedi, Maaruf Ali (2019). The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications. Annals of Emerging Technologies in Computing, 3(3), 19-27. https://europub.co.uk/articles/-A-594476