The Efficient Design for Error Correction in Fault Tolerant Adder Using Fpga
Journal Title: International Journal of Innovative Research in Computer Science and Technology - Year 2022, Vol 10, Issue 4
Abstract
Fault tolerant systems play a significant role in many digital systems, especially those implemented utilizing Nano scale technologies, because of their vulnerability to electromagnetic interference and transient errors brought on by cosmic rays. All digital signal processing systems and microprocessors must contain arithmetic logic circuits. The goal of the project is to construct alternative adder designs using Field Programmable Gate Arrays (FPGAs) with fault tolerance. The proposed approach consists of constructing error detection and repair schemes for the sparse Kogge-Stone adder and evaluating them against Triple Modular Redundancy methods. By utilizing the carry tree's built-in redundancy, a Kogge-Stone adder can achieve fault tolerance. By adding extra ripple carry adders into the architecture, fault tolerance is offered on a sparse Kogge-Stone adder. By inflicting faults on the ripple carry adder or in the carry tree, this fault tolerance strategy is successfully finished and confirmed on the sparse Kogge-Stone adder. The Speed "Very High Integrated Hardware Circuit Description Language" (VHDL) is used to specify the adder designs, and an FPGA is used to implement them.
Authors and Affiliations
N. Vaishnavi, SD. Afreen, M. Anjan, N. Amitha, N. Santhi Raju
Keywords
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- EP ID EP746226
- DOI 10.55524/ijircst.2022.10.4.30
- Views 49
- Downloads 0
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