VHDL Design and FPGA Implementation of a Parallel Reed-Solomon (15, K, D) Encoder/Decoder
Journal Title: International Journal of Advanced Computer Science & Applications - Year 2013, Vol 4, Issue 1
Abstract
In this article, we propose a Reed Solomon error correcting encoder/decoder with the complete description of a concrete implementation starting from a VHDL description of this decoder. The design on FPGA of the (15, k, d) Reed Solomon decoder is studied and simulated in order to implement an encoder/decoder function.The proposed architecture of the decoder can achieve a high data rate, in our case, 5 clock cycles, and having a reasonable complexity (1010 CLBs).
Authors and Affiliations
Mustapha ELHAROUSSI , Asmaa HAMYANI , Mostafa BELKASMI
Keywords
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- EP ID EP135582
- DOI 10.14569/IJACSA.2013.040105
- Views 97
- Downloads 0
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