VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate
Journal Title: International Journal of Advanced Computer Science & Applications - Year 2017, Vol 8, Issue 4
Abstract
In this work, we present a FPGA design and implementation of a parallel architecture of a low complexity LDPC decoder for high data rate applications. The selected code is a regular LDPC code (3, 4). VHDL design and synthesis of such architecture uses the decoding by the algorithm of BP (Believe propagation) simplified "Min-Sum". The complexity of the proposed architecture was studied; it is 6335 LEs at a data rate of 2.12 Gbps for quantization of 8 bits at the second iteration. We also realized a platform based on a co-simulation on Simulink to validate performance in BER (Bit Error Rate) of our architecture.
Authors and Affiliations
A. Boudaoud, M. El Haroussi, E. Abdelmounim
Keywords
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- EP ID EP258339
- DOI 10.14569/IJACSA.2017.080435
- Views 109
- Downloads 0
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