VLSI Implementation of Pipelined Fast Fourier Transform
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2012, Vol 1, Issue 4
Abstract
Digital Signal Processing (DSP) has become a very important and dynamic research area. Now a day’s many integrated circuits dedicated to DSP functions. Unfortunately Existing designs are restricted to a low accuracy and a small sample number. The Fourier transform is widely used in industrial applications as well as in scientific research. The most common use is to transform a function of time into a frequency function. In this paper, we present the efficient implementation of a pipeline FFT. Our design adopts a single-path delay feedback style as the proposed hardware architecture. To eliminate the read-only memories (ROM’s) used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT processor, thus consuming lower power than the existing works
Authors and Affiliations
K. Indirapriyadarsini , S. Kamalakumari , G. Prasannakuma
Keywords
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